1. Field of the Invention
The present invention relates generally to memory devices, and more particularly to, flash memory devices and flash memory systems.
2. Description of the Related Art
Contemporary flash memory devices and systems are less efficient than they otherwise could be. One reason for this inefficiency lies in the fact that the flash memory devices are arranged in a single array or independent smaller arrays, which operate at larger biases for typical “read” operations. For example, some known previous flash memory devices and systems require a voltage in the range of 1.8 volts to 5 volts to power the single array(s).
In addition, previous flash memory device and systems are slower than they otherwise could be. A reason for the increase time to perform their functions is due to the fact that these previous flash memory device and systems read data via a global bit line (GBL) to a sense amplifier (SA). Furthermore, performing read operations via the GBL to the SA increases parasitic loading that further limits the speed of read operations. Therefore, faster and more efficient flash memory devices and systems are desirable.